Intel promises to reduce droop with backside power in 2024
If you thought that backside power was something to do with eating too many cruciferous vegetables, think again: Intel is implementing this in future chips as a way of separating the power lines to transistors from the signal lines, simplifying chip layouts.
And to be as sure as possible that it will go well, the company has built and tested the technology via a chip manufactured using an"internal process node" based on Intel 4, the latter of which is in production now and ramping up for processors due to be launched before the end of this year.VLSI SymposiumBackside power delivery is essentially just about putting the power lines that feed the transistors onto the reverse side of the silicon wafer from which the chips are made.
The problem is that the interconnect layers have become a complex and messy web that could start to impact the performance of the chip, according to Intel, and so separating out the power lines helps to simplify things. "First of all, it's very expensive to scale these to very small dimensions, you need to use more and more UV layer to pattern these layers. You also incur higher voltage droop from the bump [external connect] all the way to the transistor, because you start to go through smaller and smaller metal lines and vias, and so the signal routing from one transistor to the other goes through various tiny little wires, and if they're too small, you incur a bigger delay," he explained.
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